1. Technical Field
Embodiments discussed herein pertain to the field of computer systems. More particularly, certain embodiments pertain to the field of high speed point-to-point interconnections and communications architectures.
2. Background Art
Computer systems include a number of components and elements. Often the components are coupled via a bus or interconnect. Peripheral Component Interconnect (PCI) is a second generation parallel bus architecture developed in 1992 as a replacement for the Industry Standard Architecture (ISA) bus. In PCI, all the devices share the same bidirectional, 32-bit (or 64-bit), parallel signal path. The PCI bus brought a number of advantages over the ISA bus, including plug-and-play operation. PCI Express (PCIe) is a third generation general-purpose serial input/output (IO) interconnect designed to replace the PCI bus. Rather than being a bus, PCIe is structured around point-to-point serial links called lanes.
In PCI/PCIe architectures, software maintains Bus/Device/Function (BDF) data structures which closely parallel the physical structure of system hardware. Plug-and-play mechanisms of PCI and PCIe support runtime insertion or removal of hardware components (and thus their functionality). However, such mechanisms are often sub-optimal with respect to operation of I/O hardware which is unlikely to be added or removed during runtime operation of a platform. This type of I/O hardware is increasingly common as manufacturing technology continues to trend toward integration, where hardware functionality which is permanently attached to, or even integrated into, the semiconductor die for a central processing unit (CPU) or other critical platform logic.
The conventional Device/Function model of PCI/PCIe for device discovery and configuration has limitations with respect to providing flexibility in mapping hardware resources to software activities. An additional problem with the PCI Device/Function model is that device discovery and configuration techniques and mechanisms are inefficient, slowing resume times from a Sleep state or other such low power states.